低功耗设计
Posted on 2015-06-18 21:42 in IC
流水线 pipeline 的艺术
Verilog HDL coding style
Posted on 2015-04-21 10:12 in IC • Tagged with Verilog, coding style
时钟生成
Posted on 2015-04-19 00:00 in IC • Tagged with clock generate unit
可配置设计
Posted on 2015-04-17 00:00 in IC • Tagged with configurable design
Verilog 的 case 小结
静态时序分析 STA 2 —— Xilinx STA
静态时序分析 STA 1 —— 基础知识
关于冒险和毛刺
Posted on 2015-03-13 21:44 in IC • Tagged with hazard, glitch
针对 Verilog 的 Doxygen
Posted on 2015-01-21 10:25 in IC • Tagged with doxygen, doxverilog, verilog